`define ALU_AND   4'b0000
`define ALU_OR    4'b0001
`define ALU_ADD   4'b0010
`define ALU_SUB   4'b0110
`define ALU_NOP   4'b1111

module alu (
  input signed [31:0] alu_in1,
  input signed [31:0] alu_in2,
  input [3:0] alu_op_ctrl,
  output reg signed [31:0] alu_result,
  output zero
);

  always @(*) begin
    case(alu_op_ctrl)
      `ALU_AND:   alu_result <= alu_in1 & alu_in2;
      `ALU_OR:    alu_result <= alu_in1 | alu_in2;
      `ALU_ADD:   alu_result <= alu_in1 + alu_in2;
      `ALU_SUB:   alu_result <= alu_in1 - alu_in2;
      `ALU_NOP:   alu_result <= alu_in1;
      default:    alu_result <= 0;
    endcase
  end
    
  assign zero = (alu_result == 32'b0);

endmodule